Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits
暂无分享,去创建一个
Marcus Völp | Thomas Mikolajick | Walter M. Weber | Andre Heinzig | Jens Trommer | Michael Raitza | Tim Baldauf
[1] G. De Micheli,et al. Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages , 2014, IEEE Transactions on Electron Devices.
[2] G. De Micheli,et al. Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.
[3] Thomas Mikolajick,et al. Dually active silicon nanowire transistors and circuits with equal electron and hole transport. , 2013, Nano letters.
[4] Dieter Fuhrmann,et al. Logical Effort Designing Fast Cmos Circuits , 2016 .
[5] Frédéric Gaffiot,et al. CNTFET Modeling and Reconfigurable Logic-Circuit Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[6] Stefan Slesazeck,et al. Material Prospects of Reconfigurable Transistor (RFETs) – From Silicon to Germanium Nanowires , 2014 .
[7] Giovanni De Micheli,et al. Novel grid-based power routing scheme for regular controllable-polarity FET arrangements , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).
[8] Stefan Slesazeck,et al. Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors , 2014, IEEE Electron Device Letters.
[9] Stefan Slesazeck,et al. Reconfigurable silicon nanowire transistors. , 2012, Nano letters.
[10] Thomas Mikolajick,et al. Direct probing of Schottky barriers in Si nanowire Schottky barrier field effect transistors. , 2011, Physical review letters.
[11] P. Lugli,et al. Non-Linear Gate Length Dependence of On-Current in Si-Nanowire FETs , 2006, 2006 European Solid-State Device Research Conference.
[12] Giovanni De Micheli,et al. A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.