A constraint based approach to automatic design of analog cells

A new system which automatically sizes and places CMOS analog cells is presented. Unlike most previous works, we have focused on general rules and algorithms which suit any type of operational amplifier. Our approach can be described in three main parts. The first part is a pattern recognizer based on electrical considerations which, given a Spice netlist, identifies basic subcircuits. This information is used in the first loop of our optimizer. Together with the target specified by the user, it results in electrical constraints used to define a good starting point in the sizing process. Classical algorithms of optimization can then be used. The same information is also an input to the placement. It results in a set of topological constraints used for the generation of the basic elements, and their relative placement. This packoge is actually used be anulog designers to quickly enter new structures and adapt them to their needs. Some design examples are reported.

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