Clocked Storage Elements
暂无分享,去创建一个
This chapter contains sections titled: On Clocking Strategy The Nonideal Nature of Clock Signals The Basic Latch-Pair The Basic Flip-Flop Rules for Robust Design��-��1 Timing Properties of Sequential Logic Comparing Latch-Pairs and Flip-Flops High-Performance Clocked Storage Elements Rules for Robust Design��-��2 Performance Metrics for Clocked Storage Elements Latching Elements for Dynamic Circuits Recommendations and Conclusion This chapter contains sections titled: References
]]>
[1] Burton M. Leary,et al. A 200 MHz 64 b dual-issue CMOS microprocessor , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[2] William J. Bowhill,et al. Design of High-Performance Microprocessor Circuits , 2001 .