An interconnection network for a novel reconfigurable circuit board

This paper presents a programmable interconnection network for a novel multi-reticle integrated circuit providing a reconfigurable circuit board for rapid system prototyping. This multi-dimensional mesh grid network, called WaferNettrade, can actively interconnect any pair of pins of integrated circuits deposited on the configurable system board. Two crossbar architectures are implemented and compared, one based on crosspoints and one based on standard cell multiplexers. Implementation results show the feasibility of this proposed cell-based array network that could interconnect a very large number of nodes, spread over an area that could fill a whole wafer, using a typical 6-metal 0.18 mum CMOS technology.

[1]  Scott A. Mahlke,et al.  BulletProof: a defect-tolerant CMP switch architecture , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[2]  Chi-Ying Tsui,et al.  A 2 Gb/s 256*256 CMOS crossbar switch fabric core design using pipelined MUX , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[3]  Pierre Marchal,et al.  Field-programmable gate arrays , 1999, CACM.

[4]  Will Moore,et al.  Wafer scale integration : proceedings of a workshop held in Southampton from 10 July to 12 July 1985 , 1986 .

[5]  Wu Jigang,et al.  Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches , 2007, IEEE Transactions on Computers.

[6]  D. Banks,et al.  Assembly and Packaging , 2006 .

[7]  Olivier Valorge,et al.  An interconnection network for a novel reconfigurable circuit board , 2009 .

[8]  Israel Koren,et al.  Defect tolerance in VLSI circuits: techniques and yield analysis , 1998, Proc. IEEE.

[9]  Yu-Liang Wu,et al.  Crossbar based design schemes for switch boxes and programmable interconnection networks , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[10]  B. Dang,et al.  Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics , 2005, IEEE Transactions on Advanced Packaging.

[11]  Joe E. Brewer.  Promise and Pitfalls of WSI , 1989 .

[12]  G. Messner,et al.  Equations for selection of cost-efficient interconnection designs , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.

[13]  Masaru Fukushi,et al.  A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches , 2004, IEEE Transactions on Instrumentation and Measurement.

[14]  Yves Blaquière,et al.  Digital signal propagation on a wafer-scale smart active programmable interconnect , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[15]  Y. Blaquiere,et al.  An active reconfigurable circuit board , 2008, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference.