Using DSP blocks for ROM replacement: a novel synthesis flow
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[1] Peter Y. K. Cheung,et al. Migrating functionality from ROMs to embedded multipliers , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.
[2] Peter J. Ashenden,et al. Programming models for hybrid CPU/FPGA chips , 2004, Computer.
[3] Jorge L. Aravena,et al. Architectures for polynomial evaluation , 1989, [1989] Proceedings. The Twenty-First Southeastern Symposium on System Theory.
[4] Steven J. E. Wilton,et al. Implementing logic in FPGA memory arrays: heterogeneous memory architectures , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..
[5] Jason Cong,et al. Performance-driven technology mapping for heterogeneous FPGAs , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Steven J. E. Wilton,et al. SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays , 1998, FPGA '98.
[7] T. Pavlidis,et al. Uniform piecewise polynomial approximation with variable joints , 1974 .