CDM ESD current characterization — Package variability effects and comparison to die-level CDM
暂无分享,去创建一个
Javier A. Salcedo | Thorsten Weyl | Alan W. Righter | Andrew H. Olney | J. Salcedo | A. Righter | A. Olney | T. Weyl
[1] Sung-Mo Kang,et al. Chip-level simulation for CDM failures in multi-power ICs , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).
[2] W. John,et al. Electrical characterisation of a power SO-package in the context of electrostatic discharge , 2003, 2003 IEEE International Symposium on Electromagnetic Compatibility, 2003. EMC '03..
[3] Melanie Etherton. Charged Device Model (CDM) ESD in ICs , 2006 .
[4] L.G. Henry,et al. Different CDM ESD Simulators provide different failure thresholds from the same device even though all the simulators meet the CDM standard specifications , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.
[5] Yuanzhong Zhou,et al. Effect of large device capacitance on FICDM peak current , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
[6] C. Duvvury,et al. CDM peak current variations and impact upon CDM performance thresholds , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
[7] Wolfgang Stadler,et al. CDM tests on interface test chips for the verification of ESD protection concepts , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
[8] K. Rinne,et al. Dynamic-Adaptive Field Induced Charged Device Model (FICDM) compact tester model , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
[9] J.A. Salcedo,et al. Electrostatic discharge protection framework for mixed-signal high voltage CMOS applications , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
[10] M. Fakhruddin,et al. Effect of flip-chip package parameters on CDM discharge , 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.
[11] Karl Rinne,et al. ESD event simulation automation using automatic extraction of the relevant portion of a full chip , 2009, 2009 10th International Symposium on Quality Electronic Design.