DEVELOPMENT OF VERIFICATION IP OF LIN CONTROLLER USING VERIFICATION METHODOLOGY MANUAL

Verification has become one of the time consuming task in design and verification cycle and hence takes up the major chunk of the resources. In order to meet the quality of verification which decides the success of the design, verification teams around the world adopt different verification methodologies, which are a systematic way of verifying design with a rich set of standard rules and guidelines. Since the serial communication protocols are preferred means of data communication, application of Verification Methodology Manual (VMM) environment for the verification of LIN controller has tremendous implementation scope. In the present work, VMM has been followed as the methodology for the development of verification environment and functional verification of LIN controller. VMM Class Library provides the building blocks needed to quickly develop reusable and well-constructed verification components and test environments using SystemVerilog. Few changes are made in the sequences generated and the timing for driving of the control signals for a particular module through minor changes in the code rather than developing all the classes for the verification environment from the scratch. The work introduces a directed stimulus generating testing environment for the design which includes generator, driver, monitor and checker. Based on the environment created, data packets were generated by the generator and transmitted to the LIN controller. These data packets are transmitted by the transmitter of LIN controller and verified at the receiver in the verification environment.