CAD tools for the synthesis, verification, and testability of robust asynchronous circuits

Although many applications could benefit from the advantages of asynchronous circuits, the time-to-market pressures faced by industry designers force the use of synchronous design styles for which numerous mature computer-aided-design (CAD) tools are available. Recently, however, heightened interest in low power consumption and growing concern over clock skew has encouraged the use of asynchronous techniques as a viable approach to future circuit design. This thesis details our developments in the synthesis, verification, and testability of speed-independent circuits, a class of asynchronous circuits guaranteed to function correctly regardless of individual gate delays. We use a state graph as a specification language because of its compatibility with a variety of high-level languages, allowing the designer to choose between several specification formats. We developed a synthesis tool that generates correct gate-level speed-independent circuits suitable for standard-cell and gate-array implementations. The synthesized circuits are on average approximately 25% faster and 5% smaller when compared to circuits in which delay elements are added to avoid circuit hazards. Although most synthesis methods ensure correct circuits by construction, verification has proven to be a necessary part of the design cycle because it provides a means of debugging synthesis tools and checking hand optimizations. We have developed a verification tool that implements an efficient conservative verification algorithm which has exponentially lower complexity than traditional tools. Experimental results on a large benchmark of circuits taken from industry and academia demonstrate that, in practice, our tool yields no false negatives, verifies large circuits that can not be verified using traditional tools, and verifies small circuits up to two or three orders of magnitude faster than traditional tools. In addition, we addressed the testability property of such circuits, including discovering a self-checking property of speed-independent circuits for multiple output stuck-at-faults. This thesis describes an integrated approach to the computer-aided design of speed-independent circuits, making asynchronous circuits a feasible alternative to more traditional synchronous circuits.