Impact of Complex Logic Cell Layout on the Single-Event Transient Sensitivity

The design methodology based on standard cells is widely used in a broad range of very-large-scale integration (VLSI) applications. Furthermore, several optimization algorithms can be employed to address different constraints such as power consumption or reliability. This paper evaluates the implications of the usage of complex logic cells from a 45-nm standard-cell library to the single-event transient (SET) sensitivity under heavy ions. Results show that even though a reduction in the layout area is obtained when adopting complex logic gates, a slight reduction in the total sensitive area of the circuit is observed. Moreover, the effectiveness of the logical masking can be suppressed, leading to a higher SET cross section for high particle linear energy transfer (LET).

[1]  L. Dilillo,et al.  Determining Realistic Parameters for the Double Exponential Law that Models Transient Current Pulses , 2014, IEEE Transactions on Nuclear Science.

[2]  P E Dodd,et al.  Current and Future Challenges in Radiation Effects on CMOS Electronics , 2010, IEEE Transactions on Nuclear Science.

[3]  Massimo Alioto,et al.  Comparative soft error evaluation of layout cells in FinFET technology , 2014, Microelectron. Reliab..

[4]  Fernanda Gusmão de Lima Kastensmidt,et al.  Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology , 2017, Microelectron. Reliab..

[5]  Paul D. Franzon,et al.  FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[6]  Dan Alexandrescu,et al.  A Practical Approach to Single Event Transient Analysis for Highly Complex Design , 2011, Journal of Electronic Testing.

[7]  Gracieli Posser,et al.  Reducing the number of transistors with gate clustering , 2016, 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS).

[8]  B.L. Bhuva,et al.  Charge Collection and Charge Sharing in a 130 nm CMOS Technology , 2006, IEEE Transactions on Nuclear Science.

[9]  Guillaume Hubert,et al.  Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation , 2015, Integr..

[10]  R.A. Reed,et al.  Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection , 2008, IEEE Transactions on Nuclear Science.

[11]  K. Banerjee,et al.  A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations , 2007, IEEE Transactions on Electron Devices.

[12]  Jürgen Koehl,et al.  Standard-cell-based design methodology for high-performance support chips , 1997, IBM J. Res. Dev..

[13]  P. Eaton,et al.  Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits , 2009, IEEE Transactions on Nuclear Science.

[14]  A. Lindoso,et al.  Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits , 2011, IEEE Transactions on Nuclear Science.

[15]  Kartik Mohanram,et al.  Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  P. E. Dodd,et al.  Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.

[17]  J.-L. Autran,et al.  Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions , 2018, Microelectron. Reliab..

[18]  Mateus Fogaça,et al.  Drive Strength Aware Cell Movement Techniques for Timing Driven Placement , 2016, ISPD.

[19]  M. Cabanas-Holmen,et al.  Heavy Ion and High Energy Proton-Induced Single Event Transients in 90 nm Inverter, NAND and NOR Gates , 2009, IEEE Transactions on Nuclear Science.

[20]  E. Lorfèvre,et al.  The Power Law Shape of Heavy Ions Experimental Cross Section , 2017, IEEE Transactions on Nuclear Science.

[21]  Ricardo Reis.  Power consumption & reliability in NanoCMOS , 2011, 2011 11th IEEE International Conference on Nanotechnology.

[22]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[23]  Frédéric Saigné,et al.  MC-ORACLE: A tool for predicting Soft Error Rate , 2011, Comput. Phys. Commun..

[24]  Mateus Fogaça,et al.  Quadratic timing objectives for incremental timing-driven placement optimization , 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).