Advanced Functional Decomposition Using Majority and Its Applications

Typical operators for the decomposition of Boolean functions in state-of-the-art algorithms are AND, exclusive-OR (XOR), and the 2-to-1 multiplexer (MUX). We propose a logic decomposition algorithm that uses the majority-of-three (MAJ) operation. Such a decomposition can extend the capabilities of current logic decompositions, but only found limited attention in the previous work. Our algorithm make use of a decomposition rule based on MAJ. Combined with disjoint-support decomposition, the algorithm can factorize XOR-majority graphs (XMGs), a recently proposed data structure which has XOR, MAJ, and inverters as only logic primitives. XMGs have been applied in various applications, including: 1) exact-synthesis-aware rewriting; 2) preoptimization for 6-input look-up table (6-LUT) mapping; and 3) synthesis of quantum circuits. An experimental evaluation shows that our algorithm leads to better XMGs compared to state-of-the-art algorithms based on XMGs, which positively affects all of these three applications. As one example, our experiments show that the proposed method achieves an average of 10% and 26% reduction on the LUTs size/depth product applied to the EPFL arithmetic and random control benchmarks after technology mapping, respectively.

[1]  Giovanni De Micheli,et al.  Finding all simple disjunctive decompositions using irredundant sum-of-products forms , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[2]  Elena Dubrova,et al.  AIG rewriting using 5-input cuts , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[3]  A. Brayton.  Faster Logic Manipulation for Large Designs , 2012 .

[4]  Karem A. Sakallah,et al.  Optimal Combinational Multi-Level Logic Synthesis , 2009 .

[5]  Giovanni De Micheli,et al.  Majority-Inverter Graph: A New Paradigm for Logic Optimization , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Mathias Soeken,et al.  SAT Based Exact Synthesis using DAG Topology Families , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[7]  Mathias Soeken,et al.  SAT-Based Combinational and Sequential Dependency Computation , 2016, Haifa Verification Conference.

[8]  Eiichi Goto,et al.  Some Theorems Useful in Threshold Logic for Enumerating Boolean Functions , 1962, IFIP Congress.

[9]  Malgorzata Marek-Sadowska,et al.  Multilevel logic synthesis for arithmetic functions , 1996, 33rd Design Automation Conference Proceedings, 1996.

[10]  Grigory Yaroslavtsev,et al.  Finding Efficient Circuits Using SAT-Solvers , 2009, SAT.

[11]  Yoshihiro Tohma,et al.  Decompositions of Logical Functions Using Majority Decision Elements , 1964, IEEE Trans. Electron. Comput..

[12]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Giovanni De Micheli,et al.  Busy man's synthesis: Combinational delay optimization with SAT , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[14]  M. Mitchell Waldrop,et al.  The chips are down for Moore’s law , 2016, Nature.

[15]  R. Karp.  Functional Decomposition and Switching Circuit Design , 1963 .

[16]  Donald E. Knuth.  The Art of Computer Programming, Volume 4, Fascicle 6: Satisfiability , 2015 .

[17]  Robert K. Brayton,et al.  Boolean factoring and decomposition of logic networks , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[18]  Karem A. Sakallah,et al.  Resynthesis of multi-level circuits under tight constraints using symbolic optimization , 2002, ICCAD 2002.

[19]  Robert K. Brayton,et al.  Improvements to Technology Mapping for LUT-Based FPGAs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Giovanni De Micheli,et al.  Optimizing Majority-Inverter Graphs with functional hashing , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[21]  Sheldon B. Akers,et al.  Synthesis of combinational logic using three-input majority gates , 1962, SWCT.

[22]  Sze-Tsen Hu.  ON THE DECOMPOSITION OF SWITCHING FUNCTIONS , 1961 .

[23]  R. A. Smith.  Minimal Three-Variable NOR and NAND Logic Circuits , 1965, IEEE Trans. Electron. Comput..

[24]  Zhiru Zhang,et al.  A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping , 2017, FPGA.

[25]  H. A. Curtis,et al.  A new approach to The design of switching circuits , 1962 .

[26]  Alan Mishchenko.  An Approach to Disjoint-Support Decomposition of Logic Functions , 2001 .

[27]  Giovanni De Micheli,et al.  Majority-Inverter Graph: A novel data-structure and algorithms for efficient logic optimization , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[28]  Giovanni De Micheli,et al.  Classifying Functions with Exact Synthesis , 2017, 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL).

[29]  Giovanni De Micheli,et al.  Design automation and design space exploration for quantum computers , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[30]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[31]  Mathias Soeken,et al.  Exact Synthesis of Majority-Inverter Graphs and Its Applications , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  M. Kostylev,et al.  Realization of spin-wave logic gates , 2007, 0711.4720.

[33]  A. Mishchenko.  Enumeration of Irredundant Circuit Structures , 2014 .

[34]  A. Kitaev,et al.  Universal quantum computation with ideal Clifford gates and noisy ancillas (14 pages) , 2004, quant-ph/0403025.

[35]  Giovanni De Micheli,et al.  BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[36]  Giovanni De Micheli,et al.  Functional decomposition using majority , 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

[37]  Luca Benini,et al.  Decision Diagrams and Pass Transistor Logic Synthesis , 1997 .

[38]  Maciej J. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2000, DAC.

[39]  Valeria Bertacco,et al.  The disjunctive decomposition of logic functions , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[40]  Snider,et al.  Digital logic gate using quantum-Dot cellular automata , 1999, Science.

[41]  Sharad C. Seth,et al.  On Combinational Networks with Restricted Fan-Out , 1978, IEEE Transactions on Computers.

[42]  Robert K. Brayton,et al.  ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.

[43]  David Thomas,et al.  The Art in Computer Programming , 2001 .

[44]  Giovanni De Micheli,et al.  New Logic Synthesis as Nanotechnology Enabler , 2015, Proceedings of the IEEE.

[45]  Robert K. Brayton,et al.  Combinational and sequential mapping with priority cuts , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[46]  Giovanni De Micheli,et al.  LUT Mapping and Optimization for Majority-Inverter Graphs , 2016 .

[47]  Mayler G. A. Martins,et al.  Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

[48]  S.R. Das,et al.  On multiple fault analysis in combinational circuits by means of Boolean difference , 1976, Proceedings of the IEEE.

[49]  Giovanni De Micheli,et al.  A novel basis for logic rewriting , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[50]  A Imre,et al.  Majority Logic Gate for Magnetic Quantum-Dot Cellular Automata , 2006, Science.

[51]  Karem A. Sakallah,et al.  Constructive library-aware synthesis using symmetries , 2000, DATE '00.