论文信息 - A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist

A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist

A 14 b multi-bit ADC with a switched-capacitor pipeline architecture achieves 0.6 LSB DNL and 2 LSB INL without calibration. Typical SNR is 73 dB, while SFDR is >85 dB for input frequency up to Nyquist. The 7.8 mm/sup 2/ ADC in 0.35 μm double-poly triple-metal process operates with a 2.7 V to 3.6 V power supply, and consumes 340 mW at 3 V.

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