A folded 32-bit prefix tree adder in 0.16-/spl mu/m static CMOS

This paper presents a new prefix tree adder that is faster than previously published adder designs. The speed improvement is achieved by rearranging the logic for the computation of the sum bits in the final stage of the adder so as to exploit the differing delays with which the group-transmit, group-generate, and carries (at each and every bit position) are generated. Previous adder designs, either used group transmit signals or group propagate signals to build prefix tree for carry generation. They did not exploit the fact that in the last stage of the parallel prefix carry tree, this difference can allow rearranging of the logic for reduced logic depth. For designs where a uniform layout of the adder is not a big concern (e.g., in communication and signal processing custom chips), the negative effect of interconnect delays at the last stage of the adder can be reduced by employing a left-to-right routing of the most-significant group generate and group-transmit signals. This is useful for large word-length (greater or equal to 32) adders. Incorporating these improvements into the adder design has resulted in about 15% improvement in speed over previously proposed adder designs. A 32-bit radix-2 prefix tree adder implementation of the proposed scheme has a delay of 0.7 ns at 1.5 volts 100 C in the Lucent's 0.16-/spl mu/m static CMOS technology.