A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing Detector

Discrete-time Delta-Sigma ADCs are typically realized using switched-capacitor circuits based on operational transconductance amplifiers (OTAs). In general, OTAs are not power-efficient because of their class-A operations. Furthermore, the low DC gain of an OTA with a low supply voltage poses a challenge on the accuracy of the switched-capacitor circuits. To circumvent these problems, comparator-based switched-capacitor (CBSC) circuits have been proposed, where an OTA is substituted with a comparator and a current source. In this paper, we present an inverter-based zero-crossing detector as a replacement for the comparator in CBSC circuits. We also propose a simple 2-phase charging scheme based on charge sharing. To verify the concept, we present a second-order Delta-Sigma ADC employing the proposed zero-crossing detector circuits. The Delta-Sigma ADC designed in 180-nm CMOS technology achieves a 68-dB dynamic range with a 0.39-MHz bandwidth and consumes 600 uW from a 1.8-V power supply.

[1]  Soon-Kyun Shin,et al.  A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS , 2008, 2008 IEEE Symposium on VLSI Circuits.

[2]  Ian Galton,et al.  A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC , 2010, IEEE Journal of Solid-State Circuits.

[3]  Un-Ku Moon,et al.  A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[4]  Hae-Seung Lee,et al.  Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies , 2006, IEEE Journal of Solid-State Circuits.

[5]  Chao Chen,et al.  A 1V 14b self-timed zero-crossing-based incremental ΔΣ ADC , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[6]  Shanthi Pavan,et al.  A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications , 2008, IEEE Journal of Solid-State Circuits.

[7]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[8]  Amy Hamidah Salman,et al.  Design and implementation of DCBOTA in Delta-Sigma ADC for communication system , 2015, 2015 International Conference on Electrical Engineering and Informatics (ICEEI).

[9]  Akira Matsuzawa,et al.  A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[10]  Anne-Johan Annema,et al.  Analog circuit performance and process scaling , 1999 .