펄스 생성기를 이용한 일정한 루프 대역폭을 가지는 semi-digital, multi-channel bangbang-CDR

A semi-digital, multi-channel bangbang clock and data recovery(CDR) circuit using pulse generators which has constant loop bandwidth has been proposed. To take advantage of multi-channel architecture, a voltage controlled oscillator is shared among channels. And digital loop filter collects and processes up/down signals come from multi channels, and generates global up/down signals. To make CDR loop bandwidth constant, pulse generators have been used to adjust up/down pulse-width adaptively. Simulation results show that the loop bandwidth variation is reduced significantly. Also, by using a pulse generator, the loop filter capacitor area is significantly reduced. The proposed CDR has been implemented in 0.13um CMOS process, and occupies 1.9×1.0mm 2 chip area.