CMDL: A Class-Based Machine Description Language for Co-generation of Compilers and Simulators

Summary form only given. It is difficult to fully understand the performance of a modern dynamic programming language system, such as Java. One must observe execution in the context of specific architectures in order to evaluate the effects of optimizations. To do this we require simulators and compiler back-ends for a wide variety of machines that are capable of handling the demands of today's dynamically compiled languages and their environments. We introduce CMDL, a machine description language specifically designed for the automatic generation of simulators and compiler back-ends. CMDL is a class-based language with a C/Java style syntax aimed at extensibility. CMDL is processed by tools to generate descriptions of architectures represented in an intermediate form; the descriptions are then further combined and processed to produce efficient compiler and simulator components designed to "plug in " to existing frameworks. CMDL provides the necessary flexibility to advance the simulation paradigm to match the state of the art in computer systems.

[1]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[2]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[3]  Jack W. Davidson,et al.  Machine Descriptions to Build Tools for Embedded Systems , 1998, LCTES.

[4]  Roger Lipsett,et al.  VHDL: hardware description and design , 1989 .

[5]  Norman Ramsey,et al.  Specifying representations of machine instructions , 1997, TOPL.

[6]  R. G. G. Cattell,et al.  Automatic Derivation of Code Generators from Machine Descriptions , 1980, TOPL.

[7]  Rajiv Gupta,et al.  Automatic generation of microarchitecture simulators , 1998, Proceedings of the 1998 International Conference on Computer Languages (Cat. No.98CB36225).

[8]  Mark D. Hill,et al.  Applying programming language implementation techniques to processor simulation , 2000 .

[9]  Christopher W. Milner.  Pipeline Descriptions for Retargetable Compilers: A Decoupled Approach , 1998 .

[10]  Christopher W. Fraser,et al.  Engineering a simple, efficient code-generator generator , 1992, LOPL.

[11]  James R. Larus,et al.  Facile: a language and compiler for high-performance processor simulators , 2001, PLDI '01.

[12]  Donald E. Thomas,et al.  The Verilog® Hardware Description Language , 1990 .

[13]  Nikil D. Dutt,et al.  EXPRESSION: a language for architecture exploration through compiler/simulator retargetability , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).