Performance evaluation of new scheduling methods for the RR/RR CICQ switch

Increasing link speeds and port counts in packet switches demand that methods for minimizing internal speed-up and implementing fast scheduling be developed. Combined input and cross point queued (CICQ) switches with round-robin (RR) polling of virtual output queues (VOQ) and of cross point buffers can natively forward variable-length packets without a required internal segmentation into cells. However, native switching of variable-length packets results in unfairness between ports. To eliminate this unfairness, we propose a block transfer mechanism that transfers up to a predefined number of bytes of packet data from a selected VOQ. This mechanism does not require internal speed-up. We also propose an overlapped RR (ORR) arbiter design that fully overlaps RR polling and scheduling. Using simulation and both synthetic and traced packet traffic as input, we show that the RR/RR CICQ switch with the block transfer mechanism has a lower delay than an input queued (IQ) switch that internally uses cells. We also show that the ORR arbiter is scalable, work conserving, and fair.

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