Implementation of Low Power Flip Flop Design in Nanometer Regime

In present digital circuits, low power consumption with high packaging density is always needed. The continuous reduction of MOSFET devices channel length causes an undesirable Short Channel Effects on the device parameters rendering large power dissipation. Increased leakage current with technology improvement requires tight control. In delay flip flop the storing of data get restricted due to leakage current which can limit flip flop from performing its operation. In this paper we have illustrated Single Edge Triggered 5T Delay flip flop design with leakage reduction technique in which the feedback path get removed that was present in the conventional Delay flip flop design. The proposed design had several advantages in comparison with the conventional D FF in terms of reduced transistors count, decreased leakage current, increases stability and high speed. We have considered further the Single Edge Triggered 5T DFF design using Self Voltage Level Control Technique in Cadence Virtuoso Tool at 45 nm technology. The result shows a tremendous reduction in leakage power nearly by 68% at 1volt supply in comparison with the conventional Set-Reset latch based DFF.

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