Survey of low-power testing of VLSI circuits

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. He ends with a discussion of the opportunity to use such techniques in varying situations.

[1]  Kuen-Jong Lee,et al.  An input control technique for power reduction in scan circuits during test application , 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

[2]  Nur A. Touba,et al.  Static compaction techniques to control scan vector power dissipation , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[3]  B. Chappell.  The fine art of IC design , 1999 .

[4]  S. Chakravarty,et al.  Two techniques for minimizing power dissipation in scan circuits during test application , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[5]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[6]  Patrick Girard,et al.  Low power BIST design by hypergraph partitioning: methodology and architectures , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[7]  S. Pravossoudovitch,et al.  A gated clock scheme for low power scan testing of logic ICs or embedded cores , 2001, Proceedings 10th Asian Test Symposium.

[8]  Patrick Girard,et al.  A modified clock scheme for a low power BIST test pattern generator , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[9]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[10]  Sandeep K. Gupta,et al.  A BIST methodology for comprehensive testing of RAM with reduced heat dissipation , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[11]  Yervant Zorian,et al.  Low power/energy BIST scheme for datapaths , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[12]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 2000, J. Electron. Test..

[13]  Patrick Girard,et al.  A test vector inhibiting technique for low energy BIST design , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[14]  Paolo Prinetto,et al.  A test pattern generation methodology for low power consumption , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[15]  Sandeep K. Gupta,et al.  LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[16]  Sandeep K. Gupta,et al.  ATPG for heat dissipation minimization during test application , 1994, Proceedings., International Test Conference.

[17]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[18]  Krishnendu Chakrabarty,et al.  Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[19]  Serge Pravossoudovitch,et al.  Reducing power consumption during test application by test vector ordering , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[20]  Lee Whetsel,et al.  Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[21]  Hans-Joachim Wunderlich,et al.  BIST for systems-on-a-chip , 1998, Integr..

[22]  Kwang-Ting Cheng,et al.  Testing high speed VLSI devices using slower testers , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[23]  Sandeep K. Gupta,et al.  ATPG for heat dissipation minimization during scan testing , 1997, DAC.

[24]  Krishnendu Chakrabarty,et al.  Combining low-power scan testing and test data compression for system-on-a-chip , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[25]  Sandeep K. Gupta,et al.  DS-LFSR: a new BIST TPG for low heat dissipation , 1997, Proceedings International Test Conference 1997.

[26]  Irith Pomeranz,et al.  Techniques for minimizing power dissipation in scan and combinational circuits during test application , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Kaushik Roy,et al.  Maximum power estimation for CMOS circuits using deterministic and statistic approaches , 1996, Proceedings of 9th International Conference on VLSI Design.

[28]  Kaushik Roy,et al.  POWERTEST: a tool for energy conscious weighted random pattern testing , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[29]  Vishwani D. Agrawal,et al.  Power constraint scheduling of tests , 1994, Proceedings of 7th International Conference on VLSI Design.

[30]  Janusz Rajski,et al.  Arithmetic Built-In Self-Test for Embedded Systems , 1997 .

[31]  Patrick Girard,et al.  A test vector ordering technique for switching activity reduction during test operation , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[32]  Kuen-Jong Lee,et al.  Peak-power reduction for multiple-scan circuits during test application , 2000, Proceedings of the Ninth Asian Test Symposium.

[33]  Alfred L. Crouch,et al.  Optimization trade-offs for vector volume and test power , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[34]  R. H. Parker.  Bare die test , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[35]  Alfred L. Crouch,et al.  Design-For-Test For Digital IC's and Embedded Core Systems , 1999 .

[36]  S. Kumar,et al.  Power Dissipation During Testing: Should We Worry About it? , 1997, VTS.

[37]  Nur A. Touba,et al.  Reducing power dissipation during test using scan chain disable , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[38]  João Paulo Teixeira,et al.  Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[39]  Kaushik Roy,et al.  Maximum power estimation for CMOS circuits using deterministic and statistical approaches , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[40]  João Paulo Teixeira,et al.  Low Power BIST by Filtering Non-Detecting Vectors , 1999, European Test Workshop 1999 (Cat. No.PR00390).

[41]  Trevor York,et al.  Book Review: Principles of CMOS VLSI Design: A Systems Perspective , 1986 .

[42]  Giovanni Squillero,et al.  Low power BIST via non-linear hybrid cellular automata , 2000, Proceedings 18th IEEE VLSI Test Symposium.