Multiple-V/sub dd/ multiple-V/sub th/ CMOS (MVCMOS) for low power applications

In this paper, multiple-V/sub dd/ and multiple-V/sub th/ design techniques are combined to simultaneously achieve high performance and low power. The transistors in critical path(s) are assigned a higher supply voltage and a lower threshold voltage for high performance, while the transistors in non-critical paths may have a lower supply voltage and/or a higher threshold voltage to suppress dynamic power and leakage power. Accurate delay and power estimates using table look-up methods based on HSPICE simulations are used for supply voltage and threshold voltage optimization. Several algorithms for V/sub dd/ and V/sub th/ assignments under performance constraints are proposed and a genetic algorithm based vector control technique is presented for standby leakage reduction. For the ISCAS benchmark circuits, multiple-V/sub dd/, multiple-V/sub th/ CMOS (MVCMOS) design technique can reduce dynamic and leakage power dissipations by around 20% and 70%, respectively.