A Proposed Pipelined-Architecture for FPGA-Based Affine-Invariant Feature Detectors

This paper describes a hardware architecture for an FPGAbased implementation of affine-invariant image feature detectors, following the algorithm of Mikolajczyk & Schmid. The architecture mimics the structure of the algorithm by implementing a multi-scale Harris corner detector which feeds candidate points into an iterative procedure to determine the local affine shape of the feature’s neighbourhood (up to an undetermined rotation). Since the algorithm is iterative, and since we desire a high throughput rate, the iterations are "unrolled" into a sequence of identical computation blocks arranged in a pipeline architecture. The modularity of the resulting architecture allows for scaling the implementation to devices of different resource capacity, as well as partitioning the algorithm over several devices. The final implementation, when completed, will be part of a smart-camera system which outputs features at the same time as the associated images.