Emerging hardware cryptography and VLSI implementation

Ad-hoc network is an emerging technology for the next generation ubiquitous community. In order to keep the security of such a transient network, a practical solution is not to develop an extremely strong cipher scheme, but to explore a temporary security with practically enough cipher strength and without relying on permanent network infrastructure. Accordingly, we exploit in this study a double cipher scheme and its VLSI implementation. The double cipher scheme is an ad-hoc cipher that combines two algorithms, that is, RAC (random addressing cryptography) and data sealing. Then, the double cipher scheme is implemented as a stream cipher engine. This follows a compact multicore architecture and each core is built in the double cipher functionality. The stream cipher engine is a safety aware, high-performed single chip VLSI processor. It is developed by using a 0.18-μm standard cell CMOS technology. Prospective specifications of the chip are also described in this article.