Statistical Evaluation of Process Damage Using an Arrayed Test Pattern in a Large Number of MOSFETs

Evaluating the statistical variations of MOSFETs is important for realizing accurate analog circuits and large-scale-integration devices. A new evaluation method for the statistical variation of the electrical characteristics of MOSFETs is presented. We have developed a test circuit for understanding the statistical and local variations of MOSFETs in a very short time. We demonstrate that the electrical characteristics in more than one million MOSFETs, such as the threshold voltage and the subthreshold swing (S-Factor), are measured in 30 min and that the measured results are very efficient in developing the fabrication process, the process equipment, and the device structure to reduce the statistical and local characteristic variation.

[1]  Tadahiro Ohmi,et al.  New era of silicon technologies due to radical reaction based semiconductor manufacturing , 2006 .

[2]  Andrew R. Brown,et al.  Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs , 2001 .

[3]  M. Ieong,et al.  Monte Carlo modeling of threshold variation due to dopant fluctuations , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[4]  A.H. Montree,et al.  Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[5]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[6]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[7]  R. Keyes The effect of randomness in the distribution of impurity atoms on FET thresholds , 1975 .

[8]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[9]  M. Ieong,et al.  Modeling line edge roughness effects in sub 100 nanometer gate length devices , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[10]  G. Ghibaudo,et al.  Impact of grain number fluctuations in the MOS transistor gate on matching performance , 2003, International Conference on Microelectronic Test Structures, 2003..

[11]  C. Mead,et al.  Fundamental limitations in microelectronics—I. MOS technology , 1972 .

[12]  Willy Sansen,et al.  An easy-to-use mismatch model for the MOS transistor , 2002, IEEE J. Solid State Circuits.

[13]  B. Nauta,et al.  Analog circuits in ultra-deep-submicron CMOS , 2005, IEEE Journal of Solid-State Circuits.

[14]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[15]  A. Keshavarzi,et al.  A statistical model for extracting geometric sources of transistor performance variation , 2004, IEEE Transactions on Electron Devices.

[16]  A. Teramoto,et al.  A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs , 2009, 2009 IEEE International Conference on Microelectronic Test Structures.