Architecture evaluation for power-efficient FPGAs

This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs; (ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays; (iii) We develop a cycle-accurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power; (iv) Using the framework fpgaEVA-LP, we study the power efficiency of FPGAs, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different FPGA components and shed light on the potential opportunities of power optimization for future FPGA designs (e.g., ≤: 0.10um technology).

[1]  Altera.  Apex ii programmable logic device family data sheet , 2002 .

[2]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[3]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Li Shang,et al.  Dynamic power consumption in Virtex™-II FPGA family , 2002, FPGA '02.

[5]  Jan M. Rabaey,et al.  Low-energy embedded FPGA structures , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[6]  J. Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2000, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Kaushik Roy,et al.  Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[9]  Steven J. E. Wilton,et al.  A Flexible Power Model for FPGAs , 2002, FPL.

[10]  Malgorzata Marek-Sadowska,et al.  Efficient circuit clustering for area and power reduction in FPGAs , 2002, FPGA '02.

[11]  Wolfgang Rosenstiel,et al.  Power estimation approach for SRAM-based FPGAs , 2000, FPGA '00.

[12]  Vaughn Betz,et al.  Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[13]  Jason Cong,et al.  RASP: A General Logic Synthesis System for SRAM-Based FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[14]  Vaughn Betz,et al.  FPGA routing architecture: segmentation and buffering to optimize speed and density , 1999, FPGA '99.