Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers

Time-interleaving analog-to-digital converters (ADCs) decrease the required sampling rate for one ADC to achieve giga samples per second (GS/s) rates. The gain and timing mismatches among the ADCs generate aliasing signals, degrading the spurious-free dynamic range of the time-interleaved ADC (TI-ADC). The conventional digital correction methods for TI-ADCs have not considered an application to direct-radio-frequency (RF) sampling receivers. We present a digital correction method for bandpass sampling four-channel TI-ADCs in the receivers. The proposed method, based on a correction method for two-channel TI-ADCs, reduces the in-band aliasing signals of the four-channel TI-ADCs by using in-phase/quadrature-phase (I/Q) downconversion mixers, cascaded integrator-comb (CIC) filters, and automatic gain control (AGC) in the receiver. This allows the correction circuit including mismatch estimation to have fewer building blocks than the conventional methods: seven adders, seven multipliers, and no finite-impulse-response filters. Simulations and measurements show that the proposed method reduces the aliasing signals of 1.2 GS/s 12-bit four-channel TI-ADCs to less than −80 dBFS.

[1]  Takao Kihara,et al.  Design of cascaded integrator-comb decimation filters for direct-RF sampling receivers , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[2]  Jaewook Kim,et al.  A 1.8 to 2.4-GHz 20mW digital-intensive RF sampling receiver with a noise-canceling bandpass low-noise amplifier in 90nm CMOS , 2010, 2010 IEEE Radio Frequency Integrated Circuits Symposium.

[3]  Stephen H. Lewis,et al.  A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors , 2010, IEEE Journal of Solid-State Circuits.

[4]  Takao Kihara,et al.  Digital correction of mismatches in time-interleaved ADCs for digital-RF receivers , 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[5]  Mikko Valkama,et al.  Frequency Response Mismatches in 4-channel Time-Interleaved ADCs: Analysis, Blind Identification, and Correction , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Jaewook Kim,et al.  A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Haruo Kobayashi,et al.  Explicit analysis of channel mismatch effects in time-interleaved ADC systems , 2001 .

[8]  Mikko Valkama,et al.  Analysis, Blind Identification, and Correction of Frequency Response Mismatch in Two-Channel Time-Interleaved ADCs , 2015, IEEE Transactions on Microwave Theory and Techniques.

[9]  Mikko Valkama,et al.  Circularity-Based I/Q Imbalance Compensation in Wideband Direct-Conversion Receivers , 2008, IEEE Transactions on Vehicular Technology.

[10]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[11]  Masanori Furuta,et al.  All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Jean-Michel Hode,et al.  Correlation-Based Frequency-Response Mismatch Compensation of Quad-TIADC Using Real Samples , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.