A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure

Efficiency degradation effects of power combining transformers with partially disabled inputs are quantitatively analyzed. To improve efficiencies in lower-power modes of a multi-mode class-AB power amplifier (PA), a discrete resizing technique is introduced in combination with a parallel-combining transformer (PCT). The two-stage PA implemented in a 0.18-μm CMOS technology also includes varactor-based tunable matching circuits. The design method involves parallel-combining of two power stages, each of which are divided into three sub-cells to facilitate discrete resizing. The parallel-combining of concurrently resized power cells minimizes undesired power loss through the transformer and helps the PA to utilize the transformer efficiency maximally independent of the number of combining cells. When operating in the high-power mode, the PA exhibits a peak output power of 31 dBm with a PAE of 34.8%. Power back-offs are realized by discretely turning off parallel sub-amplifier cells concurrently, achieving output power levels of 26 dBm and 22.3 dBm with respective PAE of 22.5% and 15%. The EVM has been measured with IEEE 802.11g WLAN and 802.16e WiMAX modulated signals in three operation modes. In the high-power mode, the PA dissipates 590 mA from a 3.3 V supply.

[1]  A.M. Niknejad,et al.  A Fully Integrated Dual-Mode Highly Linear 2.4 GHz CMOS Power Amplifier for 4G WiMax Applications , 2009, IEEE Journal of Solid-State Circuits.

[2]  P. Asbeck,et al.  A 1 W 0.35 /spl mu/m CMOS power amplifier for GSM-1800 with 45% PAE , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  Ockgoo Lee,et al.  A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control , 2009, IEEE Microwave and Wireless Components Letters.

[4]  R. A. Hadaway,et al.  Monolithic transformers for silicon RF IC design , 1998, Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198).

[5]  P. Reynaert,et al.  A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE , 2005, IEEE Journal of Solid-State Circuits.

[6]  N. Wongkomet,et al.  A $+$31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications , 2006, IEEE Journal of Solid-State Circuits.

[7]  Gang Liu,et al.  Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off , 2008, IEEE Journal of Solid-State Circuits.

[8]  Kyu Hwan An,et al.  A discrete resizing and concurrent power combining structure for linear CMOS power amplifier , 2010, 2010 IEEE Radio Frequency Integrated Circuits Symposium.

[9]  S. C. Cripps,et al.  RF Power Amplifiers for Wireless Communications , 1999 .

[10]  A. Samelis,et al.  Efficiency improvement techniques at low power levels for linear CDMA and WCDMA power amplifiers , 2002, 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280).

[11]  Ockgoo Lee,et al.  Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers , 2008, IEEE Journal of Solid-State Circuits.

[12]  Gang Liu,et al.  A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[13]  Lawrence E. Larson,et al.  A 65nm CMOS 2.4GHz 31.5dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applications , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[14]  Paul R. Gray,et al.  A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications , 1999 .

[15]  D. K. Su,et al.  A CMOS RF power amplifier with parallel amplification for efficient power control , 2001 .

[16]  Howard C. Luong,et al.  A 1-V CMOS power amplifier for Bluetooth applications , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[17]  Michiel Steyaert,et al.  A 2.45-GHz 0.13-$\mu{\hbox {m}}$ CMOS PA With Parallel Amplification , 2007, IEEE Journal of Solid-State Circuits.