Memory-efficient and high-throughput decoding of quasi-cyclic LDPC codes

We propose turbo-sum-product (TSP) and shuffled-sum-product (SSP) decoding algorithms for quasi-cyclic low-density parity-check codes, which not only achieve faster convergence and better error performance than the sum-product algorithm, but also require less memory in partly parallel decoder architectures. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and may achieve a higher decoding throughput. The convergence behaviors of our TSP and SSP algorithms are also compared with those of the SP, turbo, and shuffled algorithms by their extrinsic information transfer (EXIT) charts.

[1]  H. Kfir,et al.  Parallel versus sequential updating for belief propagation decoding , 2002, cond-mat/0207185.

[2]  Hua Xiao,et al.  Graph-based message-passing schedules for decoding LDPC codes , 2004, IEEE Transactions on Communications.

[3]  Amir H. Banihashemi,et al.  Decoding Low-Density Parity-Check Codes With , 2001 .

[4]  Daniel J. Costello,et al.  LDPC block and convolutional codes based on circulant matrices , 2004, IEEE Transactions on Information Theory.

[5]  Sheng Tong,et al.  A simple convergence comparison of Gallager codes under two message-passing schedules , 2005, IEEE Commun. Lett..

[6]  Naresh R. Shanbhag,et al.  High-throughput LDPC decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Marc P. C. Fossorier,et al.  Reduced latency iterative decoding of LDPC codes , 2005, GLOBECOM '05. IEEE Global Telecommunications Conference, 2005..

[8]  Keshab K. Parhi,et al.  Overlapped message passing for quasi-cyclic low-density parity check codes , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Krishna R. Narayanan,et al.  Memory-efficient sum-product decoding of LDPC codes , 2004, IEEE Transactions on Communications.

[10]  X. Jin.  Factor graphs and the Sum-Product Algorithm , 2002 .

[11]  Stephan ten Brink,et al.  Design of low-density parity-check codes for modulation and detection , 2004, IEEE Transactions on Communications.

[12]  S. Litsyn,et al.  An efficient message-passing schedule for LDPC decoding , 2004, 2004 23rd IEEE Convention of Electrical and Electronics Engineers in Israel.

[13]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[14]  Amir H. Banihashemi,et al.  Reliability-based schedule for bit-flipping decoding of low-density Parity-check codes , 2004, IEEE Transactions on Communications.

[15]  Ning Chen,et al.  Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Juntan Zhang,et al.  Shuffled belief propagation decoding , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

[17]  Joseph R. Cavallaro,et al.  Optimized Message Passing Schedules for LDPC Decoding , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..