Clock generating circuit
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The clock generation circuit is disclosed. The clock generation circuit according to an embodiment of the present invention is a clock generator for generating a plurality of clock signal portion and comprising a duty cycle correction and outputting the plurality of corrected clock signal to compensate for the duty cycle (duty cycle) of the plurality of clock signals do. The duty cycle correcting unit and a charge pump for generating a control signal for correcting the duty cycle of the clock signal in response to the corrected clock signal. Receiving the clock signal corresponding to the duty cycle correcting unit from the plurality of amplifying sections and the plurality of amplifying parts, each for outputting the corrected clock signal duty cycle correction of the clock signal corresponding to, in response to the control signal the control signal in response to the corrected clock signal in which each output is provided with the charge pump to be applied to all of the plurality of amplification sections. The clock signal is a single-ended signal (single ended signal) or the differential signal (differential signal). The clock generation circuit according to the present invention has an advantage capable of correcting a duty error between the generated clock signal yet to reduce the current consumption, reduce the circuit area.