Dynamic Analysis of Current-Voltage Characteristics of Nanoscale Gated-Thyristors

This letter presents a detailed experimental investigation of the current-voltage characteristics of deca-nanometer gated-thyristors, highlighting that strong differences exist between the static and the dynamic operation of these devices. In particular, results reveal that the forward-breakover voltage determining thyristor turn-on does not depend only on the applied gate voltage, but also on the rise time of the applied gate pulse, decreasing for fast pulse fronts. This is explained in terms of a higher electron injection from the cathode to the anode triggering device turn-on when the gate switching time is shorter than that required for holes to leave the p-base.

[1]  A. Zaslavsky,et al.  Z2-FET: A zero-slope switching device with gate-controlled hysteresis , 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

[2]  Rajesh Gupta,et al.  32nm high-density high-speed T-RAM embedded memory technology , 2010, 2010 International Electron Devices Meeting.

[3]  F. Nemati,et al.  A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT) , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[4]  F. Nemati,et al.  A novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memories , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[5]  A. Zaslavsky,et al.  A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration , 2012, IEEE Electron Device Letters.

[6]  Rajesh Gupta,et al.  Reliability of thyristor-based memory cells , 2009, 2009 IEEE International Reliability Physics Symposium.

[7]  James D. Plummer,et al.  A novel high density, low voltage SRAM cell with a vertical NDR device , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[8]  A. Zaslavsky,et al.  A feedback silicon-on-insulator steep switching device with gate-controlled carrier injection , 2012 .

[9]  U. E. Avci,et al.  Floating-Body Diode—A Novel DRAM Device , 2012, IEEE Electron Device Letters.

[10]  V. Gopalakrishnan,et al.  Fully planar 0.562/spl mu/m/sup 2/ T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMs , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..