论文信息 - Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Several techniques to reduce the ground bounce effect in CMOS chips are described. The effective width of the predrive and final driver of a CMOS output buffer is automatically adjusted to compensate for process, voltage, and temperature (PVT) variations. The slew rate of the predrive nodes is controlled by introducing a digitally weighted capacitance. Finally, a compensated active resistance is inserted into both the power and ground leads to further dampen the oscillations. These techniques allow the buffer to behave uniformly over the entire PVT range. Measurements of a 0.5-/spl mu/m CMOS test chip have demonstrated that these new buffers generate 2.5/spl times/ less ground bounce when compared to conventional buffers. An external resistance is required to set a reference current.

T. J. Cabara | W. Fischer | J. Harrington | W. Troutman

[1] D.A. Hodges,et al. All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[2] T. J. Gabara. Reduced ground bounce and improved latch-up suppression through substrate conduction , 1988 .

[3] Douglas W. Stout,et al. VLSI performance compensation for off-chip drivers and clock generation , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[4] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .

[5] Christopher W. Branson. Integrating Tester Pin Electronics , 1990, IEEE Des. Test Comput..

[6] R. Senthinathan,et al. Noise immunity characteristics of CMOS receivers and effects of skewing/damping CMOS output driver switching waveform on the ‘simultaneous’ switching noise , 1992 .

[7] T. J. Gabara,et al. Digitally adjustable resistors in CMOS for high-performance applications , 1992 .

[8] Michael Dolle. Analysis of simultaneous switching noise , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[9] T. Gabara,et al. Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers , 1996, Proceedings of Custom Integrated Circuits Conference.

[10] T. J. Gabara. A closed-form solution to the damped RLC circuit with applications to CMOS ground bounce estimation , 1996, Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.