A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS

A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking, and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The prototype DPLL fabricated in a 90nm CMOS process operates from 0.7 to 3.5GHz. At 2.5GHz, the proposed DPLL consumes only 1.6mW power from a 1V supply and achieves 1.6ps and 11.6ps of long-term r.m.s and peak-to-peak jitter, respectively.

[1]  Chulwoo Kim,et al.  A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[2]  K. Muhammad,et al.  All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.

[3]  Ping-Ying Wang,et al.  A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes , 2009, IEEE Journal of Solid-State Circuits.

[4]  Pavan Kumar Hanumolu,et al.  Digitally-Enhanced Phase-Locking Circuits , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[5]  Jin-Sheng Wang,et al.  A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[6]  G. Temes Delta-sigma data converters , 1994 .