Transmission Line Model for Latchup in CMOS Circuits

1.0 INTRODUCTION Analysis of latchup in bulk CMOS technology begins with an equivalent circuit of the PNPN structure. Previously, lumped resistors have been used to approximate the base/emitter shunting action provided by the actual interconnection network. Although it has long been known that these shunting elements play an important role in latchup hardness, no clear and accurate technique exists for calculating these resistors in actual circuit layouts.