论文信息 - A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC

A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC

A 1.8 V 15 b 40 MS/s CMOS pipelined ADC with 90 dB SFDR and 72 dB peak SNR over the full Nyquist band is described. ADC performance is enhanced by digital background calibration of DAC noise and interstage gain error. The IC is realized in a 0.18 /spl mu/m CMOS process, consumes 400 mW, and has a die size of 4 mm/spl times/5 mm.

I. Galton | E. Siragusa

[1] Andreas Kaiser,et al. Input switch configuration suitable for rail-to-rail operation of switched-opamp circuits , 1999 .

[2] I. Mehr,et al. A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 1999, IEEE Journal of Solid-State Circuits.

[3] Ian Galton,et al. Gain error correction technique for pipelined analogue-to-digital converters , 2000 .

[4] Ian Galton. Digital cancellation of D/A converter noise in pipelined A/D converters , 2000 .