An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile

Sample interpolation which has a computationally expensive finite impulse response (FIR) digital filter is one of the key modules in MPEG-4 Advanced Simple Profile (ASP). Normal FIR architectures have low efficiency on its implementation due to the special input data stream. In this paper, based on a pure systolic FIR, the efficient VLSI architecture for the sample interpolation has been implemented. Experimental result shows that the efficiency of proposed architecture is three times higher than normal ones, and it satisfies the applications such as MPEG-4 ASP.