Node sensitivity analysis for soft errors in CMOS logic

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100 nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. Results are provided for ISCAS85 benchmark circuits

[1]  E. Normand.  Single-event effects in avionics , 1996 .

[2]  G. R. Srinivasan,et al.  Soft-error Monte Carlo modeling program, SEMM , 1996, IBM J. Res. Dev..

[3]  J. Olsen,et al.  Neutron-induced single event upsets in static RAMS observed a 10 km flight attitude , 1993 .

[4]  Quming Zhou,et al.  Transistor sizing for radiation hardening , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[5]  Yu Cao,et al.  New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[6]  M. Baze,et al.  Attenuation of single event induced pulses in CMOS combinational logic , 1997 .

[7]  R. Keith Treece,et al.  Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets , 1990, Proceedings. International Test Conference 1990.

[8]  Christer Svensson,et al.  Neutron induced soft errors in CMOS memories under reduced bias , 1998 .

[9]  James F. Ziegler,et al.  Terrestrial cosmic rays , 1996, IBM J. Res. Dev..

[10]  Russell Tessier,et al.  Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[12]  Sujit Dey,et al.  A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits , 2004, Proceedings. 41st Design Automation Conference, 2004..

[13]  Nur A. Touba,et al.  Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[14]  Y. Yagil,et al.  A systematic approach to SER estimation and solutions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[15]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[16]  N. Seifert,et al.  Radiation-induced clock jitter and race , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[17]  Christos A. Papachristou,et al.  Soft delay error effects in CMOS combinational circuits , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[18]  M. Nicolaidis,et al.  Cost reduction and evaluation of a temporary faults detecting technique , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[19]  Israel Koren,et al.  Techniques for transient fault sensitivity analysis and reduction in VLSI circuits , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[20]  E. Normand.  Single event upset at ground level , 1996 .

[21]  E. Normand,et al.  Single event upsets in implantable cardioverter defibrillators , 1998 .

[22]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[23]  E. Nonnand.  Single Event Upsets in Implantable Cardioverter Defibrillators , 1998 .

[24]  S. Vangal,et al.  Selective node engineering for chip-level soft error rate improvement [in CMOS] , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).