HOW MUCH MISMATCH SHOULD BE SIMULATED IN THE HIGH DENSITY SUM

Device mismatch in static MM (SRAM) has a strong impact to the speed yield. In this paper, a rigorous statistical model of the mismatch settings for the simulations of the sense amplifier (SA) in SUM is presented. The model comprehends the memory density, the circuit architecture, and the mismatch delay sensitivity. IN'TRODUCTION Mismatch distribution as a function of the memory density has been studied in prior work (l, 21. In this paper, a statistical model is presented to take into account of the circuit architecture and the speed mismatch sensitivity.