FAULTSIM : A fast , configurable memory-resilience simulator

Recent studies of DRAM failures in data centers and supercomputer environments have highlighted non-uniform failure modes in DRAM chips. Failures fall into different classes depending on the source of the failure (e.g., an I/O pin, rank, bank, row, column, or bit). These failures will be common in future memory technologies. To mitigate them, memory systems employ complex error correcting codes and fault repair mechanisms. One way to evaluate the relative potency of these mechanisms is with analytical models, which are time-consuming to derive. Therefore, we propose FaultSim, a configurable memory-reliability simulation tool for 2D and 3D-stacked memories. FaultSim uses Monte Carlo methods, real-world failure statistics and novel algorithms to accelerate evaluation of different resilience schemes. Using multi-granularity failure rates from field studies with BCH-1 (SECDED) and ChipKill codes, simulated results are within 0.41% and 1.13% of an approximate analytical model, respectively.