An Auto-adaptative Reconfigurable Architecture for the Control

Previous works have shown that reconfigurable architectures are particularly well-adapted for implementing regular processing applications. Nevertheless, they are inefficient for designing complex control systems. In order to solve this drawback, microprocessors are jointly used with reconfigurable devices. However, only regular, modular and reconfigurable architectures can easily take into account constant technology improvements, since they are based on the repetition of small units. This paper focuses on the self-adaptative features of a new reconfigurable architecture dedicated to the control from the application to the computation level. This reconfigurable device can itself adapt its resources to the application at run-time, and can exploit a high level of parallelism into an architecture called RAMPASS.

[1]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[2]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[3]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[4]  Th. Zahariadis,et al.  A spiral search algorithm for fast estimation of block motion vectors , 1996, 1996 8th European Signal Processing Conference (EUSIPCO 1996).

[5]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.

[6]  Stuart Swan.  An introduction to system level modeling in systemc 2 , 2001 .

[7]  G. Amdhal,et al.  Validity of the single processor approach to achieving large scale computing capabilities , 1967, AFIPS '67 (Spring).

[8]  Maya Gokhale,et al.  The NAPA adaptive processing architecture , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[9]  Herbert S. Bennett.  Compound Semiconductor Roadmap Embedded in the 2003 International Technology Roadmap for Semiconductors | NIST , 2004 .

[10]  Kunle Olukotun,et al.  REMARC : Reconfigurable Multimedia Array Coprocessor , 1999 .

[11]  Jürgen Becker,et al.  Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (CSoC) , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[12]  Gregory W. Donohoe,et al.  Low-power reconfigurable processor , 2002, Proceedings, IEEE Aerospace Conference.

[13]  Carl Ebeling,et al.  Architecture design of reconfigurable pipelined datapaths , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.

[14]  Christian Piguet,et al.  Low-Power Electronics Design , 2004 .

[15]  John Paul Shen,et al.  PipeRench implementation of the instruction path coprocessor , 2000, MICRO 33.

[16]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[17]  Wolfgang Rosenstiel,et al.  System Level Design Using the SystemC Modeling Platform , 2001 .

[18]  Nicolas Ventroux,et al.  RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems , 2004, SAMOS.

[19]  Rudy Lauwereins,et al.  Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[20]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[21]  Ivan E. Sutherland,et al.  Micropipelines , 1989, Commun. ACM.

[22]  Pascal Benoit,et al.  Highly scalable dynamically reconfigurable systolic ring-architecture for DSP applications , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[23]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[24]  Jürgen Becker,et al.  Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures , 2000, PDPTA.

[25]  Davide Rizzo,et al.  A video compression case study on a reconfigurable VLIW architecture , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.