Design of 9-transistor single bit full adder

Here, new low power single bit full adder using 9 transistors has been presented. The proposed adder has the advantage of low power consumption with less area requirements due fewer numbers of transistors. Low power goal has been achieved at circuit level by designing the adder with optimized XNOR gates and multiplexer approach. Direct path between supply voltage and ground have been minimized in the design. The circuits have been simulated in 0.18μm CMOS technology with SPICE. The adder shows power dissipation of 2.0773mW with maximum output delay of 1.86ps at supply voltage of 3.3V. Simulations have been carried out with varying supply voltage 3.3V to 2.7V. Power consumption of proposed full adder has been compared with earlier reported circuits and proposed circuit shows better results.

[1]  E. Abu-Shama,et al.  A new cell for low power adders , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[2]  Edwin Hsing-Mean Sha,et al.  A novel multiplexer-based low-power full adder , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Lizy Kurian John,et al.  A novel low power energy recovery full adder cell , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[4]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[5]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Chip-Hong Chang,et al.  A novel hybrid pass logic with static CMOS output drive full-adder cell , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[7]  M.A. Bayoumi,et al.  A structured approach for designing low power adders , 1997, Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136).

[8]  Chip-Hong Chang,et al.  A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits , 2005 .

[9]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[10]  Sung-Mo Kang,et al.  CMOS digital integrated circuits , 1995 .

[11]  Magdy A. Bayoumi,et al.  Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Ralph Etienne-Cummings,et al.  Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies , 2006, Microelectron. J..

[13]  Yingtao Jiang,et al.  Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates , 2002 .

[14]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .