Positive Bias Temperature Instability Effects in nMOSFETs With HfO 2 /TiN Gate Stacks

matters more, conclusions derived from the widely employed high-voltage stresses of short duration may no longer be valid for the much lower actual device operation bias conditions. In this paper, we propose a methodology, where a fast measurement technique for threshold voltage instability characterization (to minimize inaccuracy of the measurements due to the well-known relaxation phenomenon [9]) is combined with a fast switching modular level long-term stress capability. This approach allowed for the assessment of PBTI for a wide range of stress voltages including those very close to the transistor operational voltage. To the best of our knowledge, this is the first time such a thorough PBTI characterization is reported in the literature. We find that in addition to electron trapping into preexisting traps, trap generation processes are also activated under certain stress conditions. This observation is supported by extensive stress-induced leakage current (SILC) investigations. In the case of pronounced SILC generation effects under PBTI conditions, trap generation can be found to be the predominant VT increasing mechanism at operation conditions. Based on these findings, a two-mechanism-based semiempirical PBTI model is proposed which is found to agree well with the experimental data. Furthermore, VT instability relaxation experiments undertaken at appropriately selected bias and temperature conditions, show that the preexisting and stress-induced traps exhibit similar detrapping kinetics indicating that both types of traps may have the same physical nature. Finally, we will show that a power-law relation exists between the SILC generation and VT increase during PBTI stressing. By examining two different HKMG processes (process A and process B), it is found that this relationship is strongly process dependent. The implications of these findings are discussed in Section IV.