A Macromodeling Approach for Analog Behavior of Digital Integrated Circuits

A macromodeling technique for digital cells is presented. The proposed macromodel allows fast and accurate signal approximation, as well as delay estimation for CMOS digital circuits. To verify its accuracy, the technique is implemented on different logic gates, a half-adder, and a flip-flop. The simulation results are compared with those obtained with SPICE for a 65-nm CMOS technology with a 1.0-V power supply. The results show the delay offset and amplitude deviation are within 5% of SPICE values for an exponential input with maximum $10^{9}$ V/s slope. The execution time of the experimental simulator implemented in MATLAB was more than 1000 times faster than SPICE in all cases.

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