Quick and effective buffered legitimate skew clock routing

We propose a new quick and effective buffered legitimate skew clock routing algorithm BLST. We analyze the optimal buffer position in the clock path, and conclude the sufficient and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates topology generation, buffer insertion, and node merge together, and performs them parallel. Compared with the method of X. Zheng et al. (1999) of buffer insertion after skew clock routing, BLST improves the maximal clock delay by at least 22%. Compared with legitimate skew clock routing algorithm of M. Zhao et al. (2003) with no buffer, this algorithm further decreases the total wire length and gets from 42% to 82% reduction on the maximal clock delay. The experimental results show our algorithm is quick and effective.

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