A Fault-Tolerant Bloom Filter for Deep Packet Inspection

Bloom filters can be used for various networking applications to inspect network packet payload to search for predefined signature strings. Hardware-based bloom filters have drawn a great attention due to the fact that they provide constant lookup times at the cost of small false positives. A fault in bloom filters, however, may render the system unable to function correctly since no false negatives cannot be guaranteed. In this paper, we present a fault- tolerant bloom filter which tolerates faults in such a way that no false negatives can be guaranteed. The proposed architecture is simple enough to be implemented without any significant hardware overhead. Moreover, fault detection and recovery can be made during normal operation with negligible time overhead.

[1]  Fabrizio Lombardi,et al.  New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[3]  Jin-Fu Li,et al.  A simulator for evaluating redundancy analysis algorithms of repairable embedded memories , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[4]  Charles H. Stapper.  Simulation of spatial fault distributions for integrated circuit yield estimations , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Alexandros G. Dimakis,et al.  Network Coding for Distributed Storage Systems , 2007, IEEE INFOCOM 2007 - 26th IEEE International Conference on Computer Communications.

[6]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[7]  John W. Lockwood,et al.  Deep packet inspection using parallel bloom filters , 2004, IEEE Micro.

[8]  Pinaki Mazumder,et al.  A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Shyue-Kung Lu,et al.  Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy , 2006, 5th IEEE/ACIS International Conference on Computer and Information Science and 1st IEEE/ACIS International Workshop on Component-Based Software Engineering,Software Architecture and Reuse (ICIS-COMSAR'06).

[10]  George Varghese,et al.  Deterministic memory-efficient string matching algorithms for intrusion detection , 2004, IEEE INFOCOM 2004.

[11]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Burton H. Bloom,et al.  Space/time trade-offs in hash coding with allowable errors , 1970, CACM.

[13]  M. V. Ramakrishna,et al.  Efficient Hardware Hashing Functions for High Performance Computers , 1997, IEEE Trans. Computers.

[14]  Yervant Zorian,et al.  2001 Technology Roadmap for Semiconductors , 2002, Computer.

[15]  Evangelos P. Markatos,et al.  Exclusion-based Signature Matching for Intrusion Detection , 2002 .

[16]  Stamatis Vassiliadis,et al.  A reconfigurable perfect-hashing scheme for packet inspection , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[17]  Timothy Sherwood,et al.  A High Throughput String Matching Architecture for Intrusion Detection and Prevention , 2005, ISCA 2005.

[18]  H. Jonathan Chao,et al.  Multi-packet signature detection using prefix bloom filters , 2005, GLOBECOM '05. IEEE Global Telecommunications Conference, 2005..

[19]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[20]  Keshab K. Parhi,et al.  Low power SRAM design using hierarchical divided bit-line approach , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[21]  Yervant Zorian,et al.  Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.

[22]  Chin-Long Wey,et al.  On the Repair of Redundant RAM's , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Sy-yen Kuo,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987, IEEE Design & Test of Computers.

[24]  Andrei Broder,et al.  Network Applications of Bloom Filters: A Survey , 2004, Internet Math..

[25]  H. Shinohara,et al.  A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM , 1983, IEEE Journal of Solid-State Circuits.