论文信息 - An Interpolator for Signal Peak Detection in Front-end Electronics

An Interpolator for Signal Peak Detection in Front-end Electronics

Abstract The interpolator is designed to determine the maximum signal amplitude in the analog channel of a readout ASIC. The use of an interpolator allows to mitigate the requirements for the sampling frequency of an analog-to-digital converter built into the channel of the readout ASIC. Design process and test results of an interpolator unit implemented by means of a FPGA are described.

[1] Andreas Franck. A parallel linear-complexity implementation structure for Lagrange interpolation , 2010, The 2010 International Conference on Green Circuits and Systems.

[2] C John Moses,et al. Area efficient lagrange image up scaling architecture for multimedia applications , 2017, 2017 International Conference on Signal Processing and Communication (ICSPC).

[3] Ching-Hsuan Ma,et al. A Novel Interpolation Chip for Real-Time Multimedia Applications , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[4] Aggelos K. Katsaggelos,et al. Directionally adaptive cubic-spline interpolation using optimized interpolation kernel and edge orientation for mobile digital zoom system , 2014, The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014).

[5] Wayne Luk,et al. Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations , 2008, IEEE Transactions on Computers.

[6] Ulf Mjörnmark,et al. SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades , 2017 .

[7] E. V. Atkin,et al. Readout channel with majority logic timestamp and digital peak detector for Muon Chambers of the CBM experiment , 2016 .

[8] LiRui,et al. Image sharpening algorithm based on a variety of interpolation methods , 2012 .