SEE : a Concept for an FPGA based Emulation Engine for Spiking Neurons with Adaptive Weights

We present an FPGA based architecture of a digital acceleration platform for the simulation of spiking neurons, called Spiking Neural Network Emulation Engine (SEE), that is capable to account for up to 219 neurons with more than 3·103 weights each. This distributed memory architecture tackles the main bottle-neck of reduced memory bandwidth during the simulation of large networks of spiking neurons. With this approach an effective parallelisation of neuron modelling is achieved by providing multiple channels to the weight memory. Especially, the consideration of dynamical synapses where synaptic weights have to be adapted throughout the whole simulation time benefit from the proposed SEE architecture. The targeted programmable neuron model utilised by SEE is based on synaptic weights with several adaptation rules. It is evaluated that the currently implemented numerical integration method which is necessary for the neuron state computation can be accelerated by a factor of more than 100 compared to a software implementation running on a stand-alone PC. Key-Words: Spiking neural network, Simulation acceleration, FPGA based emulation, Numerical integration