Package induced stress impact on transistor performance for ultra-thin SoC

Integrated Circuits continuously scale including die thicknesses to achieve lower total z-height. As has been previously reported, die thinning can impact transistor performance due to mechanical stresses generated by the package. This paper is investigating the impact on the tri-gate transistors performance for die thickness below 100μm through BGA solder board attach. Ring oscillators are used to assess transistor performance with frequency data collected at wafer level, packaged unit, and board mounted levels. PMOS and NMOS effects are extracted independently using appropriately weighted oscillators. Results show that PMOS drive current increases while NMOS drive current decreases with reductions in die thickness, consistent with FEA modeling. The impact of die over-mold thickness on the transistor saturation current shifts is also included and demonstrates the importance of considering such factors in establishing the correct balance between transistor performance impact and other characteristics such as package warpage.