HotSpot Thermal Floorplan Solver Using Conjugate Gradient to Speed Up

We proposed to use the conjugate gradient method to effectively solve the thermal resistance model in HotSpot thermal floorplan tool. The iterative conjugate gradient solver is suitable for traditional sparse matrix linear systems. We also defined the relative sparse matrix in the iterative thermal floorplan of Simulated Annealing framework algorithm, and the iterative method of relative sparse matrix could be applied to other iterative framework algorithms. The experimental results show that the running time of our incremental iterative conjugate gradient solver is speeded up approximately 11x compared with the LU decomposition method for case ami49, and the experiment ratio curve shows that our iterative conjugate gradient solver accelerated more with increasing number of modules.

[1]  Andreas Günther,et al.  Numerical analysis and algorithms in control and state constrained optimization with PDEs , 2007 .

[2]  Takeshi Yoshimura,et al.  An O-tree representation of non-slicing floorplan and its applications , 1999, DAC '99.

[3]  Igor L. Markov,et al.  Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[4]  A. Pal,et al.  Methodology for thermal aware physical design , 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

[5]  Mark Po-Hung Lin.  Recent research in analog placement considering thermal gradient , 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

[6]  N. Xu,et al.  Thermal aware floorplanning using Gauss-Seidel method , 2008 .

[7]  Yu-Min Lee,et al.  ThermPL: Thermal-aware placement based on thermal contribution and locality , 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[8]  Tsuyoshi Murata,et al.  {m , 1934, ACML.

[9]  Ning Xu,et al.  Hierarchical thermal model using gauss-seidel method in floorplanning , 2007, 2007 7th International Conference on ASIC.

[10]  Philipp Birken,et al.  Numerical Linear Algebra , 2011, Encyclopedia of Parallel Computing.

[11]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[12]  Michael T. Heath,et al.  Scientific Computing: An Introductory Survey , 1996 .

[13]  Sung-Mo Kang,et al.  Cell-level placement for improving substrate thermal distribution , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[15]  Wei Liu,et al.  Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Kevin Skadron,et al.  Temperature-Aware Microarchitecture: Extended Discussion and Results , 2003 .

[17]  Yao-Wen Chang,et al.  Thermal-Driven Analog Placement Considering Device Matching , 2011, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..