ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme

The resulting capacitive load, from a large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broadband RF circuits due to the impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme, using equal four-stage ESD protection can achieve a better impedance match, but degrades the ESD performance. A new distributed ESD protection structure is proposed in this work, to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, named decreasing-size distributed ESD (DS-DESD) protection scheme, which is beneficial to the ESD level. The experimental results have shown a human-body-model (HBM) ESD robustness of up to 8 kV.

[1]  R.M.D.A. Velghe,et al.  Diode network used as ESD protection in RF applications , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[2]  B. Kleveland,et al.  Distributed ESD protection for high-speed integrated circuits , 2000, IEEE Electron Device Letters.

[3]  Kaustav Banerjee,et al.  Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs , 2002 .

[4]  P. Leroux,et al.  A 0.8 dB NF ESD-protected 9 mW CMOS LNA , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  R.W. Dutton,et al.  Analysis and optimization of distributed ESD protection circuits for high-speed mixed-signal and RF applications , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[6]  Tung-Yang Chen,et al.  ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications , 2000, IEEE Journal of Solid-State Circuits.

[7]  M. Ker Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI , 1999 .

[8]  Kaustav Banerjee,et al.  Analysis and design of ESD protection circuits for high-frequency/RF applications , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[9]  S. Wong,et al.  Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design , 2001, IEEE J. Solid State Circuits.

[10]  Paul Leroux,et al.  A 0.8 dB NF ESD-protected 9 mW CMOS LNA , 2001 .