Timing analysis with nonseparable statistical and deterministic variations

Statistical static timing analysis (SSTA) is ideal for random variations but is not suitable for environmental variations like Vdd and temperature. SSTA uses statistical approximation, according to which circuit timing is predicted accurately only for highly probable combinations of variational parameters. SSTA is not able to handle accurately deterministic sources of variation like supply voltage. This paper presents a novel technique for modeling nonseparable deterministic and statistical variations in single timing run.

[1]  Vladimir Zolotov,et al.  Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[2]  Sachin S. Sapatnekar,et al.  Statistical timing analysis considering spatial correlations using a single PERT-like traversal , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[3]  Natesan Venkateswaran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  T. Chen,et al.  Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[5]  C. E. Clark.  The Greatest of a Finite Set of Random Variables , 1961 .

[6]  D. Sylvester,et al.  A New Statistical Max Operation for Propagating Skewness in Statistical Timing Analysis , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[7]  Farid N. Najm,et al.  A Linear-Time Approach for Static Timing Analysis Covering All Process Corners , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[8]  Jinjun Xiong,et al.  Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  David Blaauw,et al.  The limit of dynamic voltage scaling and insomniac dynamic voltage scaling , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Yuhen Hu,et al.  Block based statistical timing analysis with extended canonical timing model , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[11]  P. Ghanta,et al.  A Framework for Statistical Timing Analysis using Non-Linear Delay and Slew Models , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[12]  Jinjun Xiong,et al.  Voltage binning under process variation , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[13]  Vivek De,et al.  Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors , 2002, VLSIC 2002.