Identification of critical primitive path delay faults without any path enumeration
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[1] Kwang-Ting Cheng,et al. Path selection and pattern generation for dynamic timing analysis considering power supply noise effects , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[2] Kwang-Ting Cheng,et al. Primitive delay faults: identification, testing, and design for testability , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Tsutomu Sasao,et al. Worst and Best Irredundant Sum-of-Products Expressions , 2001, IEEE Trans. Computers.
[4] Andrzej J. Strojwas,et al. Primitive path delay faults: identification and their use in timinganalysis , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Shin-ichi Minato,et al. Fast Generation of Prime-Irredundant Covers from Binary Decision Diagrams , 1993 .
[6] Spyros Tragoudas,et al. Exact path delay fault coverage with fundamental ZBDD operations , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Weiping Shi,et al. Longest-path selection for delay test under process variation , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Spyros Tragoudas,et al. Efficient identification of (critical) testable path delay faults using decision diagrams , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Kwang-Ting Cheng,et al. Critical path selection for delay fault testing based upon a statistical timing model , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[10] Spyros Tragoudas,et al. On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation , 2008, J. Electron. Test..
[11] Premachandran R. Menon,et al. Synthesis of Delay-Verifiable Combinational Circuits , 1995, IEEE Trans. Computers.
[12] Kwang-Ting Cheng,et al. Classification and identification of nonrobust untestable path delay faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..