A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

Abstract. We consider the problem of one-dimensional topological compaction with jog insertions. By combining both geometric and graph-theoretic approaches we present a faster and simpler algorithm to improve over previous results. The compaction algorithm takes as input a sketch consisting of a set F of features and a set W of wires, and minimizes the horizontal width of the sketch while maintaining its routability. The algorithm consists of the following steps: constructing a horizontal constraint graph, computing all possible jog positions, computing the critical path, relocating the features, and reconstructing a new sketch homotopic to the input sketch, which is suitable for detailed routing. The algorithm runs in O(|F| ⋅ |W|) worst-case time and space, which is asymptotically optimal in the worst case. Experimental results are also presented.

[1]  Hiroyuki Watanabe,et al.  Graph-Optimization Techniques for IC Layout and Compaction , 1983, 20th Design Automation Conference Proceedings.

[2]  Michael Ian Shamos,et al.  Computational geometry: an introduction , 1985 .

[3]  Wayne Wei-Ming Dai,et al.  Topological routing in SURF: generating a rubber-band sketch , 1991, 28th ACM/IEEE Design Automation Conference.

[4]  Chak-Kuen Wong,et al.  Single-layer global routing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Richard Cole,et al.  River Routing Every Which Way, but Loose (Extended Abstract) , 1984, FOCS.

[6]  Kurt Mehlhorn,et al.  A faster compaction algorithm with automatic jog insertion , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Chak-Kuen Wong,et al.  Global routing based on Steiner min-max trees , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  IV RobertC.Carden,et al.  A global router using an efficient approximate multicommodity multiterminal flow algorithm , 1991, 28th ACM/IEEE Design Automation Conference.

[9]  Wayne Wei-Ming Dai,et al.  Rubber band routing and dynamic data representation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.

[11]  Charles E. Leiserson,et al.  Algorithms for routing and testing routability of planar VLSI layouts , 1985, STOC '85.

[12]  Michael Kaufmann,et al.  On Steiner Minimal Trees in Grid Graphs and Its Application to VLSI Routing , 1994, ISAAC.

[13]  P. Groenveld,et al.  On Global Wire Ordering for Macro-Cell Routing , 1989, DAC.

[14]  P. Groeneveld,et al.  On Global Wire Ordering for Macro-Cell Routing , 1989, 26th ACM/IEEE Design Automation Conference.

[15]  Alfred E. Dunlop.  SLIP: symbolic layout of integrated circuits with compaction , 1978 .

[16]  Majid Sarrafzadeh,et al.  A new approach to topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Majid Sarrafzadeh,et al.  An exact algorithm for single-layer wire length minimization , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Ron Y. Pinter,et al.  River Routing: Methodology and Analysis , 1983 .

[19]  Chi-Yuan Lo,et al.  An O(n1.5logn) 1-d compaction algorithm , 1991, DAC '90.

[20]  D. T. Lee,et al.  A faster algorithm for rubber-band equivalent transformation for planar VLSI layouts , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Dana S. Richards,et al.  Complexity of Single-Layer Routing , 1984, IEEE Transactions on Computers.

[22]  F. Frances Yao,et al.  Computational Geometry , 1991, Handbook of Theoretical Computer Science, Volume A: Algorithms and Complexity.

[23]  Walter S. Scott,et al.  Magic: A VLSI Layout System , 1984, 21st Design Automation Conference Proceedings.

[24]  Majid Sarrafzadeh,et al.  An exact algorithm for single-layer wire-length minimization , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[25]  Michael Kaufmann,et al.  Advances in homotopic layout compaction , 1989, SPAA '89.

[26]  D. T. Lee,et al.  Euclidean shortest paths in the presence of rectilinear barriers , 1984, Networks.

[27]  D. T. Lee,et al.  On crossing minimization problem , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Kurt Mehlhorn,et al.  On continuous Homotopic one layer routing , 1988, SCG '88.

[29]  T. Ohtsuki,et al.  Layout design and verification , 1986 .

[30]  Malgorzata Marek-Sadowska,et al.  The crossing distribution problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[31]  Walter S. Scott,et al.  The Magic VLSI Layout System , 1985 .

[32]  Robert W. Dutton,et al.  Algorithms for optimizing, two-dimensional symbolic layout compaction , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  Kuo-Feng Liao,et al.  Boundary single-layer routing with movable terminals , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  Walter S. Scott,et al.  Plowing: Interactive Stretching and Compaction in Magic , 1984, 21st Design Automation Conference Proceedings.

[35]  Wen-Chung Kao,et al.  Cross point assignment with global rerouting for general-architecture designs , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Chak-Kuen Wong,et al.  An algorithm for optimal two-dimensional compaction of VLSI layouts , 1983, Integr..